----------------------------------------------------------------------------------
-- Company:        Johns Hopkins University
-- Engineer:       Kevin Green
-- 
-- Create Date:    23:07:12 12/02/2011 
-- Design Name:    make_lut_4
-- Module Name:    mask_lut_4 - RTL 
-- Project Name:   top_gillis_green
-- Target Devices: 
-- Tool versions: 
-- Description:    This is the 4-bit look-up table.  Given a the black and white
--                 vector, current move, and player, an output vector with the 
--                 mask positions is created.  This mask is used to clear the 
--                 opponents positions and set the players positions.
-- 
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.game_logic_pkg.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mask_lut_4 is
    Port ( black : in  STD_LOGIC_VECTOR (7 downto 0);
           white : in  STD_LOGIC_VECTOR (7 downto 0);
           player : in  STD_LOGIC;
			  move : in STD_LOGIC_VECTOR (7 downto 0);
           data_out : out  STD_LOGIC_VECTOR (7 downto 0));
end mask_lut_4;

architecture RTL of mask_lut_4 is
begin

process(black, white, player, move) is
begin
	case(player & black & white & move) is
		when '0' & x"010204" => data_out <= x"02";
		when '0' & x"010608" => data_out <= x"06";
		when '0' & x"010a04" => data_out <= x"02";
		when '1' & x"020104" => data_out <= x"02";
		when '0' & x"020408" => data_out <= x"04";
		when '1' & x"020401" => data_out <= x"02";
		when '0' & x"020508" => data_out <= x"04";
		when '1' & x"020904" => data_out <= x"02";
		when '1' & x"020c01" => data_out <= x"02";
		when '0' & x"030408" => data_out <= x"04";
		when '0' & x"040201" => data_out <= x"02";
		when '1' & x"040208" => data_out <= x"04";
		when '1' & x"040308" => data_out <= x"04";
		when '1' & x"040802" => data_out <= x"04";
		when '1' & x"040902" => data_out <= x"04";
		when '0' & x"040a01" => data_out <= x"02";
		when '1' & x"050208" => data_out <= x"04";
		when '1' & x"050802" => data_out <= x"04";
		when '1' & x"060108" => data_out <= x"06";
		when '1' & x"060801" => data_out <= x"06";
		when '0' & x"080402" => data_out <= x"04";
		when '0' & x"080502" => data_out <= x"04";
		when '0' & x"080601" => data_out <= x"06";
		when '0' & x"090204" => data_out <= x"02";
		when '0' & x"090402" => data_out <= x"04";
		when '1' & x"0a0104" => data_out <= x"02";
		when '1' & x"0a0401" => data_out <= x"02";
		when '0' & x"0c0201" => data_out <= x"02";
		when others => data_out <= x"00";
	end case;
end process;

end RTL;

